This invention relates to thin film transistors which are employed for driving pixels (i.e., picture elements) of an active matrix type flat panel display such as a liquid crystal display device, for example.
A prior art liquid crystal display device of the conventional type has a structure as shown in FIG. 1. The device comprises a pair of transparent substrates of glass or the like facing each other. A spacer 13 is provided between the substrates 11 and 12 along the edges thereof. A liquid crystal 14 is sealed between the substrates 11 and 12. The substrates 11 and 12, spacer 13 and liquid crystal 14 constitute a liquid crystal cell. A plurality of display electrodes 15 consisting of a transparent conductive film are formed on the inner surface of one of the transparent substrates, i.e., substrate 11. Also thin film transistors 16 are formed as switching elements such that they are contiguous to the display electrodes 15 with their drains connected thereto. A common electrode 17 is formed on the other transparent substrate 12. The common electrode 17 faces the plurality of display electrodes 15.
The display electrodes 15 serve as picture elements, for instance. As shown in FIG. 2, they are square in shape and arranged in a closely spaced-apart relation to one another. They are arranged in rows and columns on the transparent substrate 11. Gate buses 18 are formed such that they extend near and along the individual rows of display electrodes 15. Source buses 19 are formed such that they extend near and along the individual columns of display electrodes 15. The thin film transistors 16 noted above are formed at the intersections of the gate buses 18 and source buses 19. Each thin film transistor 16 has its gate connected to the associated gate bus 18, its source connected to the associated source bus 19 and its drain connected to the corresponding display electrode 15.
When one of the gate buses 18 and one of the source buses 19 are selected, a voltage is applied between the selected buses. As a result, only the corresponding thin film transistor 16 is turned on. Charge is stored on the display electrode 15 connected to the drain of the "on" thin film transistor 16. A voltage is applied across only a portion of the liquid crystal 14 between this display electrode 15 and the common electrode 17. Only the picture element of this display electrode 15 is thus rendered transparent or opaque. In this way, only selected display electrodes are driven for display. Actually, the picture elements of selected display electrodes are usually rendered transparent or opaque in combination with a polarizer (not shown).
Usually, the thin film transistor 16 has a structure as shown in FIGS. 3 and 4. Referring to these Figures, the display electrodes 15 and source buses 19 are formed from a transparent conductive film, e.g., an ITO, on the transparent substrate 11. A semiconductor layer 21 of amorphous silicon or the like is formed such that it strides parallel and closely spaced-apart portions of each display electrode 15 and the associated source bus 19. A gate insulating film 22 of silicon nitride or the like is formed on the semiconductor layer 21. A gate electrode 23 is formed on the gate insulating film 22 such that it overlies part of each display electrode 15 and associated source bus 19 via the gate insulating film 22 and each semiconductor layer 21. One end of the gate electrode 23 is connected to the associated gate bus 18. Portions of the display electrode 15 and source bus 19 facing each gate electrode 23 constitute drain and source electrodes 15a and 19a, respectively. The thin film transistor 16 is constituted by these electrodes 15a and 19a, the semiconductor layer 21, the gate insulating film 22 and the gate electrode 23. The individual gate electrodes 23 and gate buses 18 are formed simultaneously from aluminum, for instance.
In the conventional liquid crystal display device, electrostatic (parasitic) capacitances Cgd and Csg are formed between the gate electrode 23 of each thin film transistor 16 and its drain and source electrodes 15a and 19a, respectively. Further, a parasitic resistance Rs exists whose value depends upon the area of the semiconductor layer 21 between the gate electrode 23 and each of the drain and source electrodes 15a and 19a. The electrostatic capacitances Cgd and Csg and the parasitic resistance Rs exert a great influence on the characteristics of the thin film transistor 16. Even a slight misalignment of the gate electrode 23 relative to the semiconductor layer 21 and the drain and source electrodes 15a and 19a directly causes variations in the electrostatic capacitances Cgd and Csg, leading to dispersion in the characteristics of the thin film transistors 16. For example, in the case where the gate electrode and drain and source electrodes are designed to overlap 3 .mu.m and the width of the channel of each transistor 16 is represented by w, if they are formed as designed, then each of the electrostatic capacitances Cgd and Csg will correspond to 3w. When the gate electrode 23 shifts by 1 .mu.m toward the source electrode 19a, the electrostatic capacitances Cgd and Csg correspond to 2w and 4w, respectively. When the gate electrode 23 shifts by 2 .mu.m toward the source electrode 19a, the electrostatic capacitances Cgd and Csg correspond to 5w and w, respectively. Accordingly, such a misalignment of the gate electrode 23 seriously affects the characteristic of each thin film transistor 16. In the liquid crystal display device, dispersion in the characteristics of the thin film transistors 16 will produce variations in display.
As a solution to this problem, it may be possible to design a structure in which a second thin film transistor is connected to each display electrode at a position opposite from the afore-mentioned thin film transistor and these thin film transistors are connected in parallel to each other.
FIG. 5 schematically illustrates an example of the liquid crystal display device employing such a structure. The display electrodes 15 are arranged in a matrix form, and as in the cases of FIGS. 2 and 3, the source bus 19 is formed along one side of each column of the display electrodes 15 and connected to each display electrode 15 via the thin film transistor 16. Moreover, a thin film transistor 25 is connected to each display electrode 15 at the side opposite from the thin film transistor 16, that is, at the left of the display electrode 15 in FIG. 5. Extending along each column of the display electrodes 15 at the opposite side from the source bus 19 is another source bus 26, to which are connected source electrodes of the thin film transistors 25. The pair of source buses 19 and 26 for each column of the display electrodes 15 are interconnected at both ends, forming a loop. Though not shown, the thin film transistor 25 has its gate electrode connected to the gate bus 18 to which is connected the gate electrode of the thin film transistor 16 connected to the display electrode 15 corresponding thereto. Accordingly, the two thin film transistors 16 and 25 are connected in parallel to each other for each display electrode 15.
As depicted in FIGS. 6 and 7 in which the parts corresponding to those in FIGS. 3 and 4 are identified by the same reference numerals, each source bus 26 is formed along one side of each column of display electrodes 15 on the opposite side from the source bus 19. An amorphous silicon or like semiconductor layer 27 is extended between the source bus 26 and each display electrode 15 and is covered with the gate insulating film 22, on which a gate electrode 28 is formed, thus constituting each thin film transistor 25. The gate electrode 28 is connected to the gate bus 18.
Also in the thin film transistor 25 of the above structure, there exist an electrostatic capacitance Cgd.sub.2 at the overlapping portion between the gate electrode 28 and the display electrode 15, that is, between the gate electrode 28 and the drain electrode 15b, and an electrostatic capacitance Csg.sub.2 at the overlapping portion between the gate electrode 28 and the source bus 26, that is, between the gate electrode 28 and the source electrode 26a, as shown in FIG. 8. In this instance, however, the pair, of thin film transistors 16 and 25 are disposed on both sides of each display electrode 15 and are connected in parallel to each other. Therefore, letting the electrostatic capacitances set up between the gate electrode 23 and the display electrode 15 and the source bus 19 be represented by Cgd.sub.1 and Csg.sub.1, respectively, the electrostatic capacitances Cgd.sub.1 and Cgd.sub.2 and the electrostatic capacitances Csg.sub.1 and Csg.sub.2 are connected in parallel to each other.
Now let it be assumed that when the gate electrodes 23 and 28 overlap the drain and source electrodes as designed, the electrostatic capacitances Cgd.sub.1 +Cgd.sub.2 and Csg.sub.1 +Csg.sub.2 are each 3w, namely, that each gate electrode overlaps the drain and source electrodes 3 .mu.m and the channel width is w/2. The gate electrodes 23 and 28 of the thin film transistor 25 are formed simultaneously using the same mask; so that, for instance, when the gate electrode 23 shifts to the right-hand side in FIGS. 6, 7 and 8, the gate electrode 28 also shifts to the right-hand side by the same amount. This causes an increase in the electrostatic capacitance Csg.sub.1 between the source and gate electrodes of the thin film transistor 16, but the electrostatic capacitance Csg.sub.2 between the source and gate electrodes of the thin film transistor 25 decreases by the same amount as the amount of increase in the electrostatic capacitance Csg.sub.1. As a result of this, the source-gate capacitances of the thin film transistors 16 and 25 become 3w as designed. The same is true of the electrostatic capacitance Cgd.sub.1 between the gate and drain of the thin film transistor 16 and the electrostatic capacitance Cgd.sub.2 between the gate and drain of the thin film transistor 25; namely, an increase in one of them causes a decrease in the other, keeping their sum constant at all times. Therefore, even if the mask alignment is slightly displaced, the electrostatic capacitances can always be obtained at designed values. Accordingly, even where misalignment of the mask for forming the gate electrodes is not uniform throughout the display screen of the liquid crystal display device, thin film transistors of the same characteristics can be obtained. The sum of the parasitic resistances Rs is also constant at all times because the resistance on the side of the thin film transistor 25 decreases when the resistance on the side of the thin film transistor 16 increases.
However, in the display device of the type in which the pair of thin film transistors are connected in parallel, since the two thin film transistors are spaced apart, the bus for supplying a source or gate signal is approximately twice as long as in ordinary liquid crystal display devices, and the spacing of the source or gate buses is so small that they are often broken and short-circuited during manufacture, impairing the yield rate of fabrication of the display devices.